A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2009-11, Vol.56 (11), p.865-869
Main Authors: Xueqiang, Wang, Liyang, Pan, Dong, Wu, Chaohong, Hu, Runde, Zhou
Format: Article
Language:English
Subjects:
Chaos
Circuits
Decoders
Decoding
Delay
Error correction
Error correction codes
Error-correcting code (ECC)
fast-decoding algorithm
Flash memory
Flash memory (computers)
Galois fields
High speed
Iterative algorithms
Iterative decoding
Mathematical analysis
Microelectronics
multilevel-cell (MLC) nor flash memories
Transformations
two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder
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Summary:An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time-area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of nor flash memories.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2009.2029144