High-level synthesis of recoverable VLSI microarchitectures

Two algorithms that combine the operations of scheduling and recovery-point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit (FU) cost is minimized first and register cost second. The second algori...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 1999-12, Vol.7 (4), p.401-410, Article 401
Main Authors: Blough, D.M., Kurdahi, F.J., Seong Yong Ohm
Format: Article
Language:English
Subjects:
Algorithms
Application software
Applied sciences
Benchmarks
Central Processing Unit
Central processing units
Cost engineering
Cost function
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hardware
High level synthesis
Integrated circuits
Microarchitecture
Processor scheduling
Registers
Scheduling algorithm
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Synthesis
Very large scale integration
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Description
Summary:Two algorithms that combine the operations of scheduling and recovery-point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit (FU) cost is minimized first and register cost second. The second algorithm minimizes a weighted sum of FU and register costs. Both algorithms are optimal according to their respective cost functions and require less than 10 min of central processing unit (CPU) time on widely used high-level synthesis benchmarks. The best previous result reported several hours of CPU time for some of the same benchmarks on a computer of similar computational power.
ISSN:1063-8210
1557-9999
DOI:10.1109/92.805747