A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS

A third-order continuous-time multibit (4 bit) Delta capital sigma ADC for wireless applications is implemented in a 0.13- mu m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2005-12, Vol.40 (12), p.2416-2427
Main Authors: DÖRRER, Lukas, KUTTNER, Franz, GRECO, Patrizia, TORTA, Patrick, HARTIG, Thomas
Format: Article
Language:English
Subjects:
Applied sciences
Circuit properties
Circuits
CMOS
Counters
Delay
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Exact sciences and technology
Integrated circuits
Interpolation
Noise levels
Power consumption
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal convertors
Tracking
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Summary:A third-order continuous-time multibit (4 bit) Delta capital sigma ADC for wireless applications is implemented in a 0.13- mu m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a 4-bit flash quantizer. Moreover, the usage of a tracking ADC opens the door to a new forward-looking dynamic element matching (DEM) technique, which helps to reduce the loop delay time and consequently improves the loop stability. The SNR is 74 dB over a bandwidth of 2 MHz. The ADC consumes 3 mW from a 1.5-V supply when clocked at 104 MHz. The active area is 0.3 mm super(2).
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2005.856282