Forward-looking fault simulation for improved static compaction

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2001-10, Vol.20 (10), p.1262-1265, Article 1262
• Main Authors: Pomeranz, I., Reddy, S.M.
• Format: Article
• Language: English
• Subjects: Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Computer aided design; Computer simulation; Design engineering; Drop tests; Electrical fault detection; Fault detection; Fault diagnosis; Faults; Impact tests; Integrated circuits; Names; Sequential analysis; Sequential circuits
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/43.952743

Fault simulation of a test set in an order different from the order of generation (e.g., reverse- or random-order fault simulation) is used as a fast and effective method to drop unnecessary tests from a test set in order to reduce its size. We propose an improvement to this type of fault simulation process that makes it even more effective in reducing the test-set size. The proposed improvement allows us to drop tests without simulating them based on the fact that the faults they detect will be detected by tests that will be simulated later, hence the name of the improved procedure: forward-looking fault simulation. We present experimental results to demonstrate the effectiveness of the proposed improvement.