Packet Processing acceleration with a 3-stage programmable pipeline engine

In this letter, we present the architecture and implementation of a novel, 3-stage processing engine, suitable for deep packet processing in high-speed networks. The engine, which has been fabricated as part of a network processor, comprises of a typical RISC core and programmable hardware. To asses...

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Bibliographic Details
Published in:IEEE communications letters 2004-03, Vol.8 (3), p.183-185
Main Authors: Papaefstathiou, I., Vlachos, K., Nikolaou, N., Zervos, N., Lawrence, V.B.
Format: Article
Language:English
Subjects:
Acceleration
Application specific integrated circuits
Applied sciences
Data mining
Electronics
Engines
Exact sciences and technology
Hardness
Hardware
High speed
Integrated circuits
Integrated circuits by function (including memories and processors)
Microprocessors
Network address translation
Networks
Pipelines
Protocols
Reduced instruction set computing
RISC
Search engines
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Telecommunication traffic
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Summary:In this letter, we present the architecture and implementation of a novel, 3-stage processing engine, suitable for deep packet processing in high-speed networks. The engine, which has been fabricated as part of a network processor, comprises of a typical RISC core and programmable hardware. To assess the performance of the engine, experiments with packets of various lengths have been performed and compared against the IXP1200 network processor. The comparison has revealed that for the case study shown in this letter, the proposed packet-processing engine is up to three times faster. Moreover, the engine is simple to be fabricated, less expensive than the corresponding hardware cores of IXP1200 and can be easily programmed for different networking applications.
ISSN:1089-7798
1558-2558
DOI:10.1109/LCOMM.2004.823427