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A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling

This paper reports the development of an in-field real-time successive jitter-measurement macro whose features include 1-ps resolution jitter measurement. The newly developed jitter-measurement macro has four key features: 1) interpolated jitter oversampling; 2) a hierarchical Vernier delay line; an...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits 2006-12, Vol.41 (12), p.2911-2920
Main Authors: Nose, K., Kajita, M., Mizuno, M.
Format: Article
Language:English
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Summary:This paper reports the development of an in-field real-time successive jitter-measurement macro whose features include 1-ps resolution jitter measurement. The newly developed jitter-measurement macro has four key features: 1) interpolated jitter oversampling; 2) a hierarchical Vernier delay line; and 3)feedforward calibration, each of which helps attain high jitter-measurement resolution; as well as 4) an oversampling rate and measurement range-control technique. A test chip of the macro has been fabricated in a 90-nm process. It successfully measures small random jitter with 1-ps resolution, and large deterministic jitter can also be measured by extending the jitter-measurement range by a factor of 4
ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2006.884402