Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2006-11, Vol.25 (11), p.2502-2512
• Main Authors: Rosinger, P., Al-Hashimi, B.M., Chakrabarty, K.
• Format: Article
• Language: English
• Subjects: Algorithms; Automatic testing; Circuit testing; Complex systems; Computer aided design; Design engineering; Design for testability; Integrated circuit testing; Integrated circuits; Job shop scheduling; manufacturing testing; Optimization; Processor scheduling; reliability; Safety; Schedules; Scheduling algorithm; Studies; System on chip; System testing; System-on-a-chip; Temperature
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2006.873898

Overheating has been acknowledged as a major problem during the testing of complex system-on-chip integrated circuits. Several power-constrained test-scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the nonuniform distribution of heat dissipation across the die and the physical adjacency of simultaneously active cores. This paper proposes a new test-scheduling approach that is able to produce short test schedules and guarantee thermal safety at the same time. Two thermal-safe test-scheduling algorithms are proposed. The first algorithm computes an exact (shortest) test schedule that is guaranteed to satisfy a given maximum temperature constraint. The second algorithm is a heuristic intended for complex systems with a large number of embedded cores, for which the exact thermal-safe test-scheduling algorithm may not be feasible. Based on a low-complexity test-session thermal-cost model, this algorithm produces near-optimal length test schedules with significantly less computational effort compared to the optimal algorithm