A low-power high-performance current-mode multiport SRAM

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2001-10, Vol.9 (5), p.590-598
• Main Authors: Khellah, M.M., Elmasry, M.I.
• Format: Article
• Language: English
• Subjects: Applied sciences; Bandwidth; Circuit simulation; Clocks; CMOS process; Delay; Electric potential; Electronics; Exact sciences and technology; Integrated circuits; Integrated circuits by function (including memories and processors); Random access memory; Read-write memory; Reduction; Registers; Semiconductor device measurement; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Static random access memory; Studies; Swing; Very large scale integration; Voltage
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/92.953493

This paper presents a new approach for energy reduction and speed improvement of multiport SRAMs. The key idea is to use current-mode for both read and write operations. To toggle a memory cell, a very small voltage swing is first created on the high-capacitive bit lines. This voltage is then translated into a differential current being injected into the cell, which in turn allows complementary potential to be developed on the cell nodes. As compared to the conventional write approach, SPICE simulations using a 0.35-/spl mu/m CMOS process have shown 2.8 to 9.9/spl times/ in energy savings and 1.02 to 6.36/spl times/ reduction in delay, for memory sizes of 32 to 1 K words. We also present a current-mode sense-amplifier that operates in a similar fashion as the write circuit. The design and implementation of a pipelined 32/spl times/64 three-port register file utilizing the proposed technique is described. Measurements of the register file chip have confirmed the feasibility of the approach.