A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology

A 64-bit adder in 1.5-V/0.18- mu m partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22- mu m partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MH...

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Published in:IEEE journal of solid-state circuits 2001-10, Vol.36 (10), p.1546-1552
Main Authors: Stasiak, D.L., Mounes-Toussi, F., Storino, S.N.
Format: Article
Language:English
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Circuits
Depletion
Devices
Dynamics
Microprocessors
Noise
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cited_by cdi_FETCH-LOGICAL-c173t-b1a22e0930c963f2e793129e225a1ec7aedc1af48b4e451c6adb235bb93512fb3
cites cdi_FETCH-LOGICAL-c173t-b1a22e0930c963f2e793129e225a1ec7aedc1af48b4e451c6adb235bb93512fb3
container_end_page 1552
container_issue 10
container_start_page 1546
container_title IEEE journal of solid-state circuits
container_volume 36
creator Stasiak, D.L.
Mounes-Toussi, F.
Storino, S.N.
description A 64-bit adder in 1.5-V/0.18- mu m partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22- mu m partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits
doi_str_mv 10.1109/4.953483
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fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_1671330713</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>1671330713</sourcerecordid><originalsourceid>FETCH-LOGICAL-c173t-b1a22e0930c963f2e793129e225a1ec7aedc1af48b4e451c6adb235bb93512fb3</originalsourceid><addsrcrecordid>eNo9kLtOwzAYhT2ARClIPIJHFqf-befisaq4VKrUgctq2c4fCHKaYKdD3o1n4Jlo1YrlHB3p6Bs-Qu6AZwBcL1Smc6kqeUFmnEPFtOD8ilyn9HWYSlUwI-slVYqzIdFCMdeO1NY1RtruKGQ5e18cSBX7_enoYOPY2hAmWuMQcMSavmzXdET_uetD_zHdkMvGhoS3556Tt8eH19Uz22yf1qvlhnko5cgcWCGQa8m9LmQjsNQShEYhcgvoS4u1B9uoyilUOfjC1k7I3DktcxCNk3Nyf-IOsf_eYxpN1yaPIdgd9vtkoChBSn6M_6uPfUoRGzPEtrNxMsDN0ZBR5mRI_gHIBlbP</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1671330713</pqid></control><display><type>article</type><title>A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology</title><source>IEEE Xplore (Online service)</source><creator>Stasiak, D.L. ; Mounes-Toussi, F. ; Storino, S.N.</creator><creatorcontrib>Stasiak, D.L. ; Mounes-Toussi, F. ; Storino, S.N.</creatorcontrib><description>A 64-bit adder in 1.5-V/0.18- mu m partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22- mu m partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits</description><identifier>ISSN: 0018-9200</identifier><identifier>DOI: 10.1109/4.953483</identifier><language>eng</language><subject>Circuits ; Depletion ; Devices ; Dynamics ; Microprocessors ; Noise</subject><ispartof>IEEE journal of solid-state circuits, 2001-10, Vol.36 (10), p.1546-1552</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c173t-b1a22e0930c963f2e793129e225a1ec7aedc1af48b4e451c6adb235bb93512fb3</citedby><cites>FETCH-LOGICAL-c173t-b1a22e0930c963f2e793129e225a1ec7aedc1af48b4e451c6adb235bb93512fb3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Stasiak, D.L.</creatorcontrib><creatorcontrib>Mounes-Toussi, F.</creatorcontrib><creatorcontrib>Storino, S.N.</creatorcontrib><title>A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology</title><title>IEEE journal of solid-state circuits</title><description>A 64-bit adder in 1.5-V/0.18- mu m partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22- mu m partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits</description><subject>Circuits</subject><subject>Depletion</subject><subject>Devices</subject><subject>Dynamics</subject><subject>Microprocessors</subject><subject>Noise</subject><issn>0018-9200</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><recordid>eNo9kLtOwzAYhT2ARClIPIJHFqf-befisaq4VKrUgctq2c4fCHKaYKdD3o1n4Jlo1YrlHB3p6Bs-Qu6AZwBcL1Smc6kqeUFmnEPFtOD8ilyn9HWYSlUwI-slVYqzIdFCMdeO1NY1RtruKGQ5e18cSBX7_enoYOPY2hAmWuMQcMSavmzXdET_uetD_zHdkMvGhoS3556Tt8eH19Uz22yf1qvlhnko5cgcWCGQa8m9LmQjsNQShEYhcgvoS4u1B9uoyilUOfjC1k7I3DktcxCNk3Nyf-IOsf_eYxpN1yaPIdgd9vtkoChBSn6M_6uPfUoRGzPEtrNxMsDN0ZBR5mRI_gHIBlbP</recordid><startdate>200110</startdate><enddate>200110</enddate><creator>Stasiak, D.L.</creator><creator>Mounes-Toussi, F.</creator><creator>Storino, S.N.</creator><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope></search><sort><creationdate>200110</creationdate><title>A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology</title><author>Stasiak, D.L. ; Mounes-Toussi, F. ; Storino, S.N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c173t-b1a22e0930c963f2e793129e225a1ec7aedc1af48b4e451c6adb235bb93512fb3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Circuits</topic><topic>Depletion</topic><topic>Devices</topic><topic>Dynamics</topic><topic>Microprocessors</topic><topic>Noise</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Stasiak, D.L.</creatorcontrib><creatorcontrib>Mounes-Toussi, F.</creatorcontrib><creatorcontrib>Storino, S.N.</creatorcontrib><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology &amp; Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Stasiak, D.L.</au><au>Mounes-Toussi, F.</au><au>Storino, S.N.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><date>2001-10</date><risdate>2001</risdate><volume>36</volume><issue>10</issue><spage>1546</spage><epage>1552</epage><pages>1546-1552</pages><issn>0018-9200</issn><abstract>A 64-bit adder in 1.5-V/0.18- mu m partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22- mu m partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits</abstract><doi>10.1109/4.953483</doi><tpages>7</tpages></addata></record>
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subjects Circuits
Depletion
Devices
Dynamics
Microprocessors
Noise
title A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T21%3A22%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20440-ps%2064-bit%20adder%20in%201.5-V/0.18-%CE%BCm%20partially%20depleted%20SOI%20technology&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Stasiak,%20D.L.&rft.date=2001-10&rft.volume=36&rft.issue=10&rft.spage=1546&rft.epage=1552&rft.pages=1546-1552&rft.issn=0018-9200&rft_id=info:doi/10.1109/4.953483&rft_dat=%3Cproquest_cross%3E1671330713%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c173t-b1a22e0930c963f2e793129e225a1ec7aedc1af48b4e451c6adb235bb93512fb3%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=1671330713&rft_id=info:pmid/&rfr_iscdi=true