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A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device
A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-μm single-gate low-power SRAM device. The DOI scheme is characterized by th...
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Published in: | IEEE electron device letters 2002-12, Vol.23 (12), p.719-721 |
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container_end_page | 721 |
container_issue | 12 |
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container_title | IEEE electron device letters |
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creator | Seo, Sang-Hun Yang, Won-Suk Lee, Han-Sin Kim, Moo-Sung Koh, Kwang-Ok Park, Seung-Hyun Kim, Kyeong-Tae |
description | A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-μm single-gate low-power SRAM device. The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. Furthermore, the enhancement of CMOS transistor performance was possible by reducing the sidewall reoxidation thickness of the gate-poly Si and optimizing the implantation conditions with this technology. |
doi_str_mv | 10.1109/LED.2002.805769 |
format | article |
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The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. 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The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. 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Yang, Won-Suk ; Lee, Han-Sin ; Kim, Moo-Sung ; Koh, Kwang-Ok ; Park, Seung-Hyun ; Kim, Kyeong-Tae</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c324t-a82bd1746a092b5034963e5e6c338c581c2075c3869f7a3ce4a9511c890707773</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2002</creationdate><topic>CMOS</topic><topic>CMOS technology</topic><topic>Devices</topic><topic>Drains</topic><topic>Etching</topic><topic>Implantation</topic><topic>Leakage current</topic><topic>MOS devices</topic><topic>MOSFETs</topic><topic>Optimization</topic><topic>Optimized production technology</topic><topic>Random access memory</topic><topic>Semiconductor devices</topic><topic>Silicon</topic><topic>Space technology</topic><topic>Static random access memory</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Seo, Sang-Hun</creatorcontrib><creatorcontrib>Yang, Won-Suk</creatorcontrib><creatorcontrib>Lee, Han-Sin</creatorcontrib><creatorcontrib>Kim, Moo-Sung</creatorcontrib><creatorcontrib>Koh, Kwang-Ok</creatorcontrib><creatorcontrib>Park, Seung-Hyun</creatorcontrib><creatorcontrib>Kim, Kyeong-Tae</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Xplore (Online service)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Biotechnology Research Abstracts</collection><collection>Biotechnology and BioEngineering Abstracts</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Seo, Sang-Hun</au><au>Yang, Won-Suk</au><au>Lee, Han-Sin</au><au>Kim, Moo-Sung</au><au>Koh, Kwang-Ok</au><au>Park, Seung-Hyun</au><au>Kim, Kyeong-Tae</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2002-12-01</date><risdate>2002</risdate><volume>23</volume><issue>12</issue><spage>719</spage><epage>721</epage><pages>719-721</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>A new double offset-implanted (DOI) technology, which can effectively suppress the gate-induced drain-leakage (GIDL) current of buried-channel PMOS transistor in small-size CMOS devices, is proposed and developed with a 0.12-μm single-gate low-power SRAM device. The DOI scheme is characterized by the usage of the silicon nitride etch-stopper for the formation of borderless W-contact as offset spacer without supplementing auxiliary processes at p+ source/drain (S/D) implantation process after the n+ S/D one. It is assured that the DOI technology makes the gate-to-S/D overlap controllable, so that the GIDL current of PMOS transistor can remarkably be reduced. Furthermore, the enhancement of CMOS transistor performance was possible by reducing the sidewall reoxidation thickness of the gate-poly Si and optimizing the implantation conditions with this technology.</abstract><pub>IEEE</pub><doi>10.1109/LED.2002.805769</doi><tpages>3</tpages></addata></record> |
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subjects | CMOS CMOS technology Devices Drains Etching Implantation Leakage current MOS devices MOSFETs Optimization Optimized production technology Random access memory Semiconductor devices Silicon Space technology Static random access memory Transistors |
title | A novel double offset-implanted source/drain technology for reduction of gate-induced drain-leakage with 0.12-μm single-gate low-power SRAM device |
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