Correlator receiver architecture with PnpN optical thyristor operating as optical hard-limiter

We propose novel correlator receiver architecture with a PnpN optical thyristor operating as optical hard-limiter, and demonstrate a multiple-access interference rejection of the proposed correlator receiver. The proposed correlator receiver is composed of the 1×2 splitter, optical delay line, 2×1 c...

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Bibliographic Details
Published in:Optical Engineering 2011-07, Vol.50 (7), p.075004-075004
Main Authors: Kang, Tae-Gu, Lee, Su Ho, Park, Soonchul
Format: Article
Language:English
Subjects:
Architecture
Correlation
Decoding
Delay lines
Interference
Multiple access
Receivers
Thyristors
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Summary:We propose novel correlator receiver architecture with a PnpN optical thyristor operating as optical hard-limiter, and demonstrate a multiple-access interference rejection of the proposed correlator receiver. The proposed correlator receiver is composed of the 1×2 splitter, optical delay line, 2×1 combiner, and fabricated PnpN optical thyristor. The proposed correlator receiver enhances the system performance because it excludes some combinations of multiple-access interference patterns from causing errors as in optical code-division multiple access systems with conventional optical receiver shown in all previous works. It is found that the proposed correlator receiver can fully reject the interference signals generated by decoding processing and multiple access for two simultaneous users.
ISSN:0091-3286
1560-2303
1560-2303
DOI:10.1117/1.3599875