Parasitic capacitance removal of sub-100 nm p-MOSFETs using capacitance–voltage measurements

► C– V measurements on various gate length high-k/metal gate sub-100 nm p-MOSFETs. ► Intrinsic channel capacitance is removed. ► Method is repeated on devices simulated using Sentaurus for comparison to experimental device. ► Parasitic capacitance behavior is discussed. ► Simulated parasitic terms a...

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Bibliographic Details
Published in:Solid-state electronics 2012-02, Vol.68, p.51-55
Main Authors: Steinke, Daniel R., Piccirillo, Joseph, Gausepohl, Steven C., Vivekand, Saikumar, Rodgers, Martin P., Lee, Ji Ung
Format: Article
Language:English
Subjects:
Applied sciences
Capacitance
Channels
Computer simulation
Devices
Effective gate length
Electronics
Exact sciences and technology
Finite element method
Gates
Mathematical analysis
p-MOSFETs
Parasitic capacitance
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Transistors
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Summary:► C– V measurements on various gate length high-k/metal gate sub-100 nm p-MOSFETs. ► Intrinsic channel capacitance is removed. ► Method is repeated on devices simulated using Sentaurus for comparison to experimental device. ► Parasitic capacitance behavior is discussed. ► Simulated parasitic terms are compared to analytical models. Capacitance–voltage measurements are performed on sub-100 nm high-k/metal gate p-MOSFETs to extract the intrinsic capacitance per gate length. This is then repeated on simulated devices using finite element modeling to compare to the experimental results. The intrinsic channel capacitance for the simulated devices is isolated from the parasitic capacitance, allowing for the comparison of analytic models of parasitic capacitances to the simulation.
ISSN:0038-1101
1879-2405
DOI:10.1016/j.sse.2011.09.014