Dynamic interconnection of reconfigurable modules on reconfigurable devices

This article presents two approaches to solving the problem of communication between components dynamically placed at runtime on a reconfigurable device. The first is a circuit-routing approach designed for existing FPGAs. This approach uses the reconfigurable multiple bus (RMB). The second, network...

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Bibliographic Details
Published in:IEEE design & test of computers 2005-09, Vol.22 (5), p.443-451
Main Authors: Bobda, C., Ahmadinia, A.
Format: Article
Language:English
Subjects:
Algorithms
Chips
Clocks
Communication switching
Computer architecture
Concurrent computing
Delay
Devices
Dynamic Interconnection
Dynamics
Integrated circuit interconnections
Interconnection
Network on Chip
Network-on-a-chip
Networks
Prototyping
Reconfigurable Hardware
Reconfiguration
Routing
Runtime
Switches
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Summary:This article presents two approaches to solving the problem of communication between components dynamically placed at runtime on a reconfigurable device. The first is a circuit-routing approach designed for existing FPGAs. This approach uses the reconfigurable multiple bus (RMB). The second, network-based approach targets devices with unlimited reconfiguration capability such as coarse-grained reconfigurable devices. We introduce the dynamic network on chip (DyNoC) as a viable communication infrastructure for communication on dynamically reconfigurable devices. For prototyping the DyNoC on FPGAs, we design and implement an unrestricted communication model for a columnwise-reconfigurable chip. For the DyNoC, as well as for the RMB on chip (RMBoC), we provide algorithms and implementation results from real-life problems.
ISSN:0740-7475
2168-2356
1558-1918
2168-2364
DOI:10.1109/MDT.2005.109