Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs

Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2012-01, Vol.20 (1), p.186-191
Main Authors: Xiaoxia Wu, Wei Zhao, Nakamoto, M., Nimmagadda, C., Lisk, D., Gu, S., Radojcic, R., Nowak, M., Yuan Xie
Format: Article
Language:English
Subjects:
3-D integration
Applied sciences
Capacitance
Circuits
Delay
Design. Technologies. Operation analysis. Testing
Electric, optical and optoelectronic circuits
Electronics
Exact sciences and technology
Integrated circuit interconnections
Integrated circuit modeling
Integrated circuits
Joints
Metals
Microbumps
Microorganisms
Power consumption
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Substrates
Theoretical study. Circuits analysis and design
Three dimensional
through silicon via
Through-silicon vias
Time measurements
Very large scale integration
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Summary:Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on the circuit level. We first provide parasitic RC characteristics of intertier connections including TSV and microbumps and examine their delay. Then circuit simulation is performed to evaluate the timing impact of intertier connections.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2010.2090049