MSXmin: a modular multicast ATM packet switch with low delay and hardware complexity

We propose and analyze the architecture for a large-scale high-speed multicast switch called MSXmin. The hardware complexity of MSXmin is O(N log/sup 2/ N) which compares favorably with existing architectures. Further, the internal latency of the MSXmin is O(log/sup 2/ N) bits. While it is superior...

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Bibliographic Details
Published in:IEEE/ACM transactions on networking 2000-06, Vol.8 (3), p.407-418
Main Authors: Kannan, R., Ray, S.
Format: Article
Language:English
Subjects:
Architecture
Asynchronous transfer mode
Bandwidth
Communication switching
Complexity
Computer science
Delay
Hardware
High speed
Multicast
Packet switching
Quality of service
Routing
Switches
Tables (data)
Translations
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Summary:We propose and analyze the architecture for a large-scale high-speed multicast switch called MSXmin. The hardware complexity of MSXmin is O(N log/sup 2/ N) which compares favorably with existing architectures. Further, the internal latency of the MSXmin is O(log/sup 2/ N) bits. While it is superior to the existing architectures in terms of the hardware complexity and the internal latency, it is comparable to other multicast switches in terms of the header overhead and translation table complexity. MSXmin is output buffered and based on the group knockout principle. Moreover, MSXmin is a dual-bit-controlled tree-based switch.
ISSN:1063-6692
1558-2566
DOI:10.1109/90.851986