Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels

• Published in: International journal of circuit theory and applications 2013-07, Vol.41 (7), p.732-742
• Main Authors: Doménech-Asensi, G., Díaz-Madrid, J. A., Ruiz-Merino, R.
• Format: Article
• Language: English
• Subjects: Analog circuits; analog integrated circuits; Architecture; CMOS integrated circuits; Computer aided design; Descriptions; Hierarchies; high-level synthesis; Mathematical models; Proposals; Synthesis; VHDL-AMS
• ISSN: 0098-9886; 1097-007X
• DOI: 10.1002/cta.820

SUMMARY Some of the advantages of very high speed integrated circuits hardware description language for analog and mixed signal (VHDL‐AMS) when used to describe analog circuits are its modeling capability and the speed of simulations, in comparison with device level simulators. However, VHDL‐AMS does not allow one to complete in a systematic way the synthesis of an analog circuit from higher description levels of the design hierarchy to lower ones. This is due to the lack of CAD tools and methods for analog circuits, contrary to the situation of pure digital circuits. This is a serious drawback because it is an obstacle to its success in analog CAD tools. The proposal described in this article, on the basis of the use of parameterizable macromodels, allows a systematic and rapid translation from a VHDL‐AMS description of analog circuits to schematic level‐sized descriptions. Copyright © 2011 John Wiley & Sons, Ltd. The proposal described in this paper, based on the use of parameterizable macromodels, allows a systematic and rapid translation from a VHDL‐AMS description of CMOS analog circuits to schematic level sized descriptions. A new hierarchy levelcalled “sized architecture” is positioned between the architecture level and the cell level. A VHDL‐AMS library provides macromodels needed to link architecture and cell levels.