Towards a multiple-ISA embedded system

In these days, every new added hardware feature must not change the underlying Instruction Set Architecture (ISA), in order to avoid adaptation or recompilation of existing code. Binary translation (BT) allows the execution of already compiled applications on different architectures. Therefore, it o...

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Bibliographic Details
Published in:Journal of systems architecture 2013-02, Vol.59 (2), p.103-119
Main Authors: Fajardo, Jair, Rutzig, Mateus B., Carro, Luigi, Beck, Antonio C.S.
Format: Article
Language:English
Subjects:
Architecture
Arrays
Assembly
Binary system
Binary translation
Code optimization
Computer architecture
Dynamical systems
Dynamics
Embedded systems
Hardware
Legacy
Programming languages
Reconfigurable architecture
Studies
Systems design
Translations
Transparent execution
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Summary:In these days, every new added hardware feature must not change the underlying Instruction Set Architecture (ISA), in order to avoid adaptation or recompilation of existing code. Binary translation (BT) allows the execution of already compiled applications on different architectures. Therefore, it opens new possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues. To overcome the BT inherent performance penalty, we propose a new mechanism based on a dynamic two-level binary translation system. While the first level is responsible for the BT de facto to an intermediate machine language, the second level optimizes the already translated instructions to be executed on the target architecture. The system is totally flexible: it supports the porting of radically different ISAs and the employment of different target architectures. This paper presents the first effort towards this direction: it translates code implemented in the x86 ISA to MIPS assembly (the intermediate language), which will be optimized by the target architecture: a dynamically reconfigurable array. We show that it is possible to maintain binary compatibility, with performance improvements and no energy losses, when compared to native execution.
ISSN:1383-7621
1873-6165
DOI:10.1016/j.sysarc.2012.10.001