A New Improved MCML Logic for DPA Resistant Circuits

Security of electronic data remains the major concern. The art of encryption to secure the data can be achieved in various levels of abstraction. The choice of the logic style to implement the security algorithms has increased significance, which impact in providing resistance to side channel attack...

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Bibliographic Details
Published in:International journal of VLSI design & communication systems 2013-10, Vol.4 (5), p.63-75
Main Authors: A.K, Tripathy, A, Prathiba, V.S, Kanchana Bhaaskaran
Format: Article
Language:English
Subjects:
Algorithms
Channels
Circuits
CMOS
Electronics
Gates
Logic
Sustainability
Online Access:Get full text
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Summary:Security of electronic data remains the major concern. The art of encryption to secure the data can be achieved in various levels of abstraction. The choice of the logic style to implement the security algorithms has increased significance, which impact in providing resistance to side channel attacks. The conventional CMOS circuits proved to be prone to side channel power attacks, the exploration of current mode logic for its sustainability against all these attacks is discussed in this article. Various characteristics of the current mode logic styles, which make it suitable for making DPA resistant circuits are explored. Logic gates such as XOR, NAND and AND of both the MCML families and CMOS circuits are designed and compared for the side channel resistance. A distributed arrangement of sleep transistors towards reducing the static power dissipation in the logic gates is also proposed, designed and analyzed. All the logic gates in MCML and CMOS were implemented, using standard 180 nm CMOS technology employing Cadence EDA tools.
ISSN:0976-1527
0976-1357
DOI:10.5121/vlsic.2013.4505