Booth Multiplier using Reversible Logic with Low Power and Reduced Logical Complexity

The proposed testable reversible architecture scheme yields significantly reduced complexity, low power and high speed features. It is a key issue in the interface of computation and physics, and of growing importance as miniaturization progresses towards its physical limits. With the advent of nano...

Full description

Saved in:
Bibliographic Details
Published in:Indian journal of science and technology 2014-04, Vol.7 (4), p.525-529
Main Author: Nandal, Amita
Format: Article
Language:English
Subjects:
Algorithms
Circuits
Complexity
Design engineering
High speed
Logic
Multipliers
Power consumption
Citations: Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The proposed testable reversible architecture scheme yields significantly reduced complexity, low power and high speed features. It is a key issue in the interface of computation and physics, and of growing importance as miniaturization progresses towards its physical limits. With the advent of nanotechnology, the fault detection and testability is of high interest for accuracy. This research work describes the reversible testable design of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm can be used to accelerate the multiplication speed with reduced power consumption. The resultant multiplier circuit shows better performance than others, and can be used in the systems requiring very high performance. The proposed booth multiplier design shows 12% reduced logical complexity, 10% reduced power consumption and efficient device utilization achieved in comparison to existing reversible logic.
ISSN:0974-6846
0974-5645
DOI:10.17485/ijst/2014/v7i4.15