Nano Scale Low Power Chopper Amplifier using Cascode and Miller Compensation Nutrilization in 45 nm CMOS

• Published in: International journal of computer applications 2015-01, Vol.112 (3)
• Main Authors: Sharma, Lavlesh, Akashe, Shyam
• Format: Article
• Language: English
• Subjects: Amplifiers; Choppers; CMOS; Computer simulation; Low pass filters; Noise; Offsets; Power consumption
• ISSN: 0975-8887; 0975-8887
• DOI: 10.5120/19650-1251

In this paper, reduced power consumption, low-noise CMOS amplifier using chopper technique is designed, chopper-equalized amplifier had been used as a front end of a voltage-to-frequency converter instrument which performs pretty well, and they were meeting just about every specification, but they had a problem with undesired and unpleasant little offset shifts and jumps. Trying to solve this problem of the jumpy offset, Chopping technique proved to be an efficient approach to decrease the low-frequency offset and 1/f noise of amplifiers. The chopper amplifier consist of combination of two-stage amplifier . The first stage is by the introduction of cascade amplifier produces high output impedance to the amplifier and the equivalent Miller capacitance of the second stage amplifier constitute to reduce the modulating noise by introduction of low pass filter in a attainable objective to gain the required Performa, so the chopper amplifier need low-pass filter, which can decrease the power consumption. The circuit of the proposed chopper amplifier is designed and simulated with cadence 45nm CMOS process and at a supply voltage 0. 7V. Simulation results shows that the equivalent input noise is 23nV/ Hz at 100 Hz and the power consumption is 102 Watt.