Ultra high density 3D via RRAM in pure 28nm CMOS process

In this paper, we present an ultra high density 3D Via RRAM with 28nm HKMG CMOS fully compatible process. It is the first time to report a cross-point 3D RRAM formed by the stacked 30nm × 30nm Cu Via and Cu metal line of 28nm HKMG CMOS Cu single damascene process. The 3D Via RRAM cell consists of a...

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Bibliographic Details
Main Authors: Min-Che Hsieh, Yu-Cheng Liao, Yung-Wen Chin, Chen-Hsin Lien, Tzong-Sheng Chang, Yue-Der Chih, Natarajan, Sreedhar, Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin
Format: Conference Proceeding
Language:English
Subjects:
CMOS
CMOS integrated circuits
Compatibility
Computer architecture
Copper
Devices
Electrodes
High density
Meetings
Metals
Microprocessors
Three dimensional
Three-dimensional displays
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Summary:In this paper, we present an ultra high density 3D Via RRAM with 28nm HKMG CMOS fully compatible process. It is the first time to report a cross-point 3D RRAM formed by the stacked 30nm × 30nm Cu Via and Cu metal line of 28nm HKMG CMOS Cu single damascene process. The 3D Via RRAM cell consists of a TaON-based resistive film, Cu Via as top electrode, and Cu metal as bottom electrode. The TaON-based RRAM film is a composite layer of backend metal glue layer of Ta and TaN in 28nm Cu damascene process. Moreover, in the compact 3D Via RRAM structure, the unit area of a single stacked cell-string is reduced to only 4 times of Via size by 28nm CMOS design rules. Since the cross-point 3D Via RRAM is fabricated without extra TMO film or process step, this excellent cell scalability and compatibility can provide a competitive low cost and high density embedded NVM solution in advanced CMOS logic nodes.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.2013.6724600