Modular integration of annular TSV structures filled with tungsten in a 0.25μm SiGe:C BiCMOS technology

• Published in: Microelectronic engineering 2015-04, Vol.137, p.153-157
• Main Authors: Marschmeyer, S., Berthold, J., Krüger, A., Lisker, M., Scheit, A., Schulze, S., Trusch, A., Wietstruck, M., Wolansky, D.
• Format: Article
• Language: English
• Subjects: Annular; Annular TSVs filled tungsten; Bonding; High frequencies; Metal oxide semiconductors; Oxides; Plasma induced damage; Semiconductor devices; Transistors; TSV fabrication; TSV integration; Tungsten
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2014.09.020

[Display omitted] •Annular TSV structures filled with tungsten were integrated in a BiCMOS technology.•The impact of TSV fabrication on the performance of MOS transistors was investigated.•MOS transistors were controlled by measurement of characteristic electrical parameters.•Hot carrier injection tests were done to stress gate oxide of MOS transistors.•The TSVs were fabricated without any effect on MOS transistors. The through silicon via (TSV) technology is a key solution for enhancement of functionality and performance of integrated chips. The replacement of bond wires by TSVs is a new possibility to create a low parasitic ground for high frequency applications. Therefore, we implemented TSVs filled with tungsten in our high frequency 0.25μm SiGe:C BiCMOS technology. Here, we demonstrate our concept for integration of annular TSVs with a depth of 75μm and a width of 3μm. Due to the many additional plasma processes for the TSV fabrication, we controlled the validity of the gate oxide of MOS transistors by measurement of electrical parameters which are sensitive to plasma induced damage (PID). Additionally, we performed hot carrier injection (HCI) test. But we did not found any difference in the performance of the MOS transistors depending on TSV fabrication.