Area and performance study of FinFET with detailed parasitic capacitance analysis in 16nm process node

An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay ti...

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Bibliographic Details
Main Authors: Okagaki, T., Shibutani, K., Matsushita, H., Ojiro, H., Morimoto, M., Tsukamoto, Y., Nii, K., Onozawa, K.
Format: Conference Proceeding
Language:English
Subjects:
Capacitance
Conferences
Delay
Devices
Facsimile
Interconnections
Leakage current
Logic gates
Microelectronics
Utilization
Online Access:Request full text
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Summary:An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay time with simple layout modification only. Moreover, small number of delay cell can reduce a leakage current in a chip.
ISSN:1071-9032
2158-1029
DOI:10.1109/ICMTS.2015.7106125