A 4 GHz CMOS multiplier for sigma-delta modulated signals

An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has als...

Full description

Saved in:
Bibliographic Details
Published in:Journal of semiconductors 2014, Vol.35 (1), p.91-95
Main Author: 郭晓丹 孟桥 梁勇
Format: Article
Language:English
Subjects:
Chips
CMOS
CMOS工艺
Delay
Electric potential
GHz
High speed
Logic
Multipliers
Semiconductors
sigma-delta调制
乘数
调制信号
逻辑技术
集成电路设计
高速乘法器
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:An integrated circuit design of a high speed multiplier for direct sigma-delta modulated bit-stream signals is presented. Compared with conventional structures, this multiplier reduces the circuit-loop delay of its sub-modules and works efficiently at a high speed. The multiplier＇s stability has also been improved with source coupled logic technology. The chip is fabricated in a TSMC 0.18-μm CMOS process. The test results demonstrate that the chip realizes the multiplication function and exhibits an excellent performance. It can work at 4 GHz and the voltage output amplitude reaches the designed maximum value with no error bit caused by logic race-and-hazard. Additionally, the analysis of the multiplier＇s noise performance is also presented.
ISSN:1674-4926
DOI:10.1088/1674-4926/35/1/015003