Radiation hard programmable delay line for LHCb calorimeter upgrade

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter fr...

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Bibliographic Details
Published in:Journal of instrumentation 2014-01, Vol.9 (1), p.C01016-C01016, Article C01016
Main Authors: Mauricio, J, Gascón, D, Vilasís, X, Picatoste, E, Machefert, F, Lefrancois, J, Duarte, O, Beigbeder, C
Format: Article
Language:English
Subjects:
Chips
Clocks
Delay
Delay lines
Dynamic link libraries
Electronics
Jitter
Noise
Phase shift
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Summary:This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm super(2) chip has been implemented in CMOS 0.35 mu m technology.
ISSN:1748-0221
1748-0221
DOI:10.1088/1748-0221/9/01/C01016