A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies

In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed ST cell which uses high and low V[subTH] transistors to improve the read and write stability. To enhance th...

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Bibliographic Details
Published in:Integration (Amsterdam) 2015-06, Vol.50, p.91-106
Main Authors: Ansari, Mohammad, Afzali-Kusha, Hassan, Ebrahimi, Behzad, Navabi, Zainalabedin, Afzali-Kusha, Ali, Pedram, Massoud
Format: Article
Language:English
Subjects:
Effectiveness
Electric potential
Semiconductor devices
Simulation
Stability
Static random access memory
Transistors
Voltage
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Summary:In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed ST cell which uses high and low V[subTH] transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) white keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 rim, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The study shows that the proposed cell meets the required cell sigma value (6[sigma]) under all conditions.
ISSN:0167-9260
DOI:10.1016/j.vlsi.2015.02.002