A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS

This paper presents a quad-lane serial link that supports virtually all data center system-side and line-side communications standards from 8.5-13 Gbps, implemented in 28 nm CMOS. The Tx is series source terminated with a 4-tap FFE. Its swing ranges from 33 mV to 1 Vppd. The Rx has CTLE, 5-tap DFE a...

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Main Authors: Ali, Tamer, Rao, Lakshmi, Singh, Ullas, Abdul-Latif, Mohammed, Yang Liu, Hafez, Amr Amin, Park, Henry, Vasani, Anand, Zhi Huang, Iyer, Arvindh, Bo Zhang, Momtaz, Afshin, Kocaman, Namik
Format: Conference Proceeding
Language:English
Subjects:
Calibration
Circuits
CMOS
CMOS integrated circuits
Consumption
Decision feedback equalizers
Impedance
Links
Noise levels
Nyquist frequencies
Serials
Timing
Transceivers
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Summary:This paper presents a quad-lane serial link that supports virtually all data center system-side and line-side communications standards from 8.5-13 Gbps, implemented in 28 nm CMOS. The Tx is series source terminated with a 4-tap FFE. Its swing ranges from 33 mV to 1 Vppd. The Rx has CTLE, 5-tap DFE and CDR with 2x-oversampling, and baud-rate timing recovery options. At 13 Gbps, the link can equalize 35 dB loss at Nyquist frequency with BER of 10 -12 . The link consumes 49 mW per lane at 13 Gbps. This is the lowest reported power in its class to date, and with comprehensive programmability for a wide range of standards.
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2015.7231318