A low specific on-resistance SOI LDMOS with a novel junction field plate

• Published in: Chinese physics B 2014-07, Vol.23 (7), p.686-690
• Main Authors: Luo, Yin-Chun, Luo, Xiao-Rong, Hu, Gang-Yi, Fan, Yuan-Hang, Li, Peng-Cheng, Wei, Jie, Tan, Qiao, Zhang, Bo
• Format: Article
• Language: English
• Subjects: Blocking; Breakdown; Electric potential; Electrical junctions; LDMOS; Oxides; P-N结; Plates (structural members); SOI; Tradeoffs; Voltage; 低导通电阻; 击穿电压; 场板; 电荷补偿; 表面电场
• ISSN: 1674-1056; 2058-3834; 1741-4199
• DOI: 10.1088/1674-1056/23/7/077306

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.