VLSI Architecture Design of FM0/Manchester Codec With 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications

• Published in: IEEE sensors journal 2015-12, Vol.15 (12), p.6875-6889
• Main Authors: Lee, Yu-Hsuan, Pan, Cheng-Wei, Tsai, Fang-Hsu
• Format: Article
• Language: English
• Subjects: Codec; Codecs; Decoding; Design engineering; DSRC; Encoding; FM0 code; Hardware; Hardware utilization rate (HUR); Manchester; Manchester code; Sensors; Transistors; Very large scale integration; VLSI; Xenon
• ISSN: 1530-437X; 1558-1748
• DOI: 10.1109/JSEN.2015.2464712

Dedicated short-range communication (DSRC) plays an important role in sensor networking for intelligent transportation system applications. How to achieve a higher hardware efficiency becomes an attractive issue to design each critical building bock in sensor node. DSRC standards usually adopt either FM0 code or Manchester code as a coding technique to enhance signal reliability. In this paper, a fully reused VLSI architecture of FM0/Manchester codec with a hardware utilization rate (HUR) of 100% is proposed for DSRC-based sensor node. It is based on the half-cycle processing model (HCPM). The HCPM includes three core techniques: 1) half-cycle logic partition; 2) reused-based retiming; and 3) Boolean function reshaping. The HCPM can improve the HUR of FM0/Manchester codec from 27.33% to 100% with the reduction of the transistor count from 86 to 66. A 100% HUR means every transistor is activated; therefore, a more power is consumed. With a design tradeoff between HUR and power consumption, this paper still presents a higher energy efficiency. This paper is realized in TSMC 0.18-μm 1P6M CMOS technology. The silicon area of core circuit is 33 × 120 μm 2 . The experiment results demonstrate that this paper presents a competitive performance with 100% HUR compared with the existing works. With this paper, DSRC-based sensor nodes can present a 100% HUR FM0/Manchester codec, fully supporting DSRC standards of Europe, USA, and Japan.