A 13bits 4.096GHz 45nm CMOS digital decimation filter chain with Carry-Save format numbers

In this paper we analyze the architecture of a 13bits 4.096GHz multi-stage decimation filter for multi-standard radio receivers. It also explores the benefits of Carry-Save format numbers in this decimation filter. After trading off between area and power consumption, we propose to use shift-and-add...

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Bibliographic Details
Published in:Microprocessors and microsystems 2015-11, Vol.39 (8), p.869-878
Main Authors: Huang, Yanxiang, Kapoor, Ajay, Rutten, Robert, Pineda de Gyvez, José
Format: Article
Language:English
Subjects:
Architecture
Carry-Save number
Chains
CMOS
Computer arithmetic
Decimation filter
Format
Hardware
Microprocessors
Power consumption
Signal processing
Tradeoffs
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Summary:In this paper we analyze the architecture of a 13bits 4.096GHz multi-stage decimation filter for multi-standard radio receivers. It also explores the benefits of Carry-Save format numbers in this decimation filter. After trading off between area and power consumption, we propose to use shift-and-adder for high data rate decimation stages and hardware multiply-accumulator for low data rate stages. The proposed decimation filter chain exploits the advantage of all architectures and exhibit the best area-power trade-off. It is implemented using 45nm CMOS technology. The proposed design reduces power by 13.7% without area overhead, compared with a conventional filter chain using only binary number.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2014.11.003