Merge Mode Estimation for a Hardware-Based HEVC Encoder

High Efficiency Video Coding (HEVC) is a video coding standard that offers higher performance than previous video coding standards such as H.264/AVC. Merge mode is one of the new tools adopted in HEVC to improve the inter-frame coding efficiency. Merge mode saves the bits for the motion vector (MV)...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology 2016-01, Vol.26 (1), p.195-209
Main Authors: Kim, Tae Sung, Rhee, Chae Eun, Lee, Hyuk-Jae
Format: Article
Language:English
Subjects:
Coders
Coding
Coding standards
Computation
Computational complexity
Encoders
Encoding
Gate counting
Gates
Hardware
Hardware Organization
High-Efficiency Video Coding (HEVC)
Interpolation
Memory management
Merge Mode Estimation
Motion compensation
Motion simulation
Random access memory
Video coding
Video Compression
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Summary:High Efficiency Video Coding (HEVC) is a video coding standard that offers higher performance than previous video coding standards such as H.264/AVC. Merge mode is one of the new tools adopted in HEVC to improve the inter-frame coding efficiency. Merge mode saves the bits for the motion vector (MV) by sharing the MV with neighboring blocks. Merge mode estimation (MME) is the process of finding a merge mode candidate, which requires extensive computations and memory accesses due to the associated motion compensation. Although MME is very similar to motion estimation (ME) in many ways, previous research on ME cannot be directly applied to solve many difficulties in designing MME hardware. In this paper, the characteristics of and the computational complexity involved in MME are discussed. To improve the throughput of the MME hardware, partially increased parallelism is efficiently exploited. Furthermore, the M-of-N-pixel combination and flexible memory access schemes are proposed to maximize the scalability to support various block sizes of HEVC and to reduce the time for fetching reference data. The proposed schemes are applied to the MME hardware design in this paper. The proposed hardware can process 56074 of 64 × 64 coding tree units per second with a clock frequency of 366 MHz, and its gate count is 585.4k with 2 kB of dual-port static RAM.
ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2015.2496820