Hardware/software co-design of power level difference based noise cancellation

In this paper, the Power Level Difference (PLD)-based noise cancelling algorithm is implemented in a Xilinx FPGA SoC using hardware/software co-design methodology. Thanks to the hardware/software co-design, the complex control part of the algorithm can be fast deployed in software meanwhile the comp...

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Bibliographic Details
Main Authors: Phu Ha, Van, Nguyen, Duc Minh, Dang, Quang Hieu
Format: Conference Proceeding
Language:English
Subjects:
Algorithms
Co-design
Computer programs
Conferences
Electric power generation
FPGA
Hardware
Hardware/Software Co-Design
Microphones
Noise
Noise cancellation
Partitioning algorithms
Software
Software algorithms
Speech
Verilog
Online Access:Request full text
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Description
Summary:In this paper, the Power Level Difference (PLD)-based noise cancelling algorithm is implemented in a Xilinx FPGA SoC using hardware/software co-design methodology. Thanks to the hardware/software co-design, the complex control part of the algorithm can be fast deployed in software meanwhile the computational part is effectively implemented in hardware. Therefore, the system can not only process the real-time input data but also consumes few hardware resource.
ISSN:2162-1020
2162-1039
DOI:10.1109/ATC.2015.7388404