Classic and alternative methods of p-type doping 4H-SiC for integrated lateral devices

P-type 4H-SiC layers formed by ion implantation need high temperature process generating surface roughness, losing and incomplete activation of dopants. Due to dopant redistribution and channeling effect, it is difficult to predict the depth of the formed junctions. Vapor-Liquid-Solid (VLS) selectiv...

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Bibliographic Details
Main Authors: Lazar, M., Carole, D., Raynaud, C., Ferro, G., Sejil, S., Laariedh, F., Brylinski, C., Planson, D., Morel, H.
Format: Conference Proceeding
Language:English
Subjects:
Annealing
Conferences
Devices
Dopants
Electrodes
Ion implantation
JFET
Junctions
RIE
Rough surfaces
Semiconductors
Silicon carbide
Surface roughness
Temperature measurement
VLS epitaxial growth
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Summary:P-type 4H-SiC layers formed by ion implantation need high temperature process generating surface roughness, losing and incomplete activation of dopants. Due to dopant redistribution and channeling effect, it is difficult to predict the depth of the formed junctions. Vapor-Liquid-Solid (VLS) selective epitaxy is an alternative method to obtain locally highly doped p-type layers in the 1020 cm-3 range or more. The depth of this p-type layers or regions is accurately controlled by the initial Reactive-Ion-Etching (RIE) of the SiC. Lateral Junction Field Effect Transistor (JFET) devices are fabricated integrating p-type layers created by Al ion implantation or VLS growth. The P-type VLS layers improve the access resistances on the electrodes of the fabricated devices.
ISSN:1545-827X
2377-0678
DOI:10.1109/SMICND.2015.7355190