Electrical properties of SiO2/SiC interfaces on 2 degree -off axis 4H-SiC epilayers

In this paper, the electrical properties of the SiO2/SiC interface on silicon carbide (4H-SiC) epilayers grown on 2 degree -off axis substrates were studied. After epilayer growth, chemical mechanical polishing (CMP) allowed to obtain an atomically flat surface with a roughness of 0.14nm. Metal-oxid...

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Bibliographic Details
Published in:Applied surface science 2016-02, Vol.364, p.892-895
Main Authors: Vivona, M, Fiorenza, P, Sledziewski, T, Krieger, M, Chassagne, T, Zielinski, M, Roccaforte, F
Format: Article
Language:English
Subjects:
Breakdown
Density
Devices
Electrical properties
Mechanical polishing
MOSFETs
Silicon carbide
Silicon dioxide
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Summary:In this paper, the electrical properties of the SiO2/SiC interface on silicon carbide (4H-SiC) epilayers grown on 2 degree -off axis substrates were studied. After epilayer growth, chemical mechanical polishing (CMP) allowed to obtain an atomically flat surface with a roughness of 0.14nm. Metal-oxide-semiconductor (MOS) capacitors, fabricated on this surface, showed an interface state density of 11012 eV-1 cm-2 below the conduction band, a value which is comparable to the standard 4 degree -off-axis material commonly used for 4H-SiC MOS-based device fabrication. Moreover, the Fowler-Nordheim and time-zero-dielectric breakdown analyses confirmed an almost ideal behavior of the interface. The results demonstrate the maturity of the 2 degree -off axis material for 4H-SiC MOSFET device fabrication.
ISSN:0169-4332
DOI:10.1016/j.apsusc.2015.12.006