CMOS fully integrated reconfigurable power amplifier with efficiency enhancement for LTE applications

A fully integrated power amplifier using a power cell switching technique, implemented in 65 nm CMOS technology is presented. The main objective of the proposed architecture is to significantly improve the efficiency at high power back-off. To do so, distributed active transformers are used as the s...

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Bibliographic Details
Published in:Electronics letters 2015-01, Vol.51 (2), p.181-183
Main Authors: Tuffery, A, Deltimple, N, Kerhervé, E, Knopik, V, Cathelin, P
Format: Article
Language:English
Subjects:
Architecture
Bias
CMOS
CMOS fully integrated reconfigurable power amplifier
CMOS integrated circuits
combiner
DC bias feed
distributed active transformer
efficiency enhancement
Engineering Sciences
frequency 2.5 GHz
high power back‐off
impedance convertors
Long Term Evolution
Low level
LTE application
Micro and nanotechnologies
Microelectronics
parallelised power cell
Partitions
Power amplifiers
power cell switching technique
size 65 nm
splitter
Switching
Transformers
Wireless communications
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Summary:A fully integrated power amplifier using a power cell switching technique, implemented in 65 nm CMOS technology is presented. The main objective of the proposed architecture is to significantly improve the efficiency at high power back-off. To do so, distributed active transformers are used as the splitter, the combiner and the DC bias feed to partition the power requirements among the parallelised power cells. An individual cell can be dynamically turned ON/OFF according to the desired output power. At 2.5 GHz, the measured maximum output power is 28.2 dBm and the power-added efficiency is improved for low level, +3.2 and +4.9% for 18 and 23.7 dBm, respectively.
ISSN:0013-5194
1350-911X
1350-911X
DOI:10.1049/el.2014.3525