DESIGN OF LOW POWER SINGLE STAGE FOLDED CASCODE CMOS OPERATIONAL AMPLIFIER FOR PIPELINE ANALOG-TO-DIGITAL CONVERTER

This work presents a low power single stage folded cascode CMOS operational amplifier (op-amp) implemented in 0.13 mu m CMOS Silterra technology. This op-amp will intended for pipeline analog-to-digital converter (ADC). The proposed op-amp is employed folded cascode topology for obtaining a high DC...

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Bibliographic Details
Published in:ARPN journal of engineering and applied sciences 2015-10, Vol.10 (18), p.8330-8332
Main Authors: Ishak, Izatul Syafina, Murad, Sohiful Anuar Zainol, Bakar, Faizah Abu
Format: Article
Language:English
Subjects:
Amplification
CMOS
Converters
Gain
Operational amplifiers
Pipelines
Settling
Unity
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Summary:This work presents a low power single stage folded cascode CMOS operational amplifier (op-amp) implemented in 0.13 mu m CMOS Silterra technology. This op-amp will intended for pipeline analog-to-digital converter (ADC). The proposed op-amp is employed folded cascode topology for obtaining a high DC gain and fast settling with high unity gain. The NMOS input differential pair is used to obtain larger output gain. The simulation results show that the op-amp achieved DC gain of 64.5 dB and unity gain bandwidth (UGB) of 133.1 MHz at 1.8 V supply voltage. Moreover, the cut-off frequency of 95.62 MHz is attained. A 1 pF load capacitor is applied in performing a stable phase margin of 68.4[degrees]. The slew rate of 22.6 V/ mu s with 72.4 ns settling time is obtained with a 0.3 mW of power consumption.
ISSN:1819-6608
1819-6608