A LOW POWER AND AREA EFFICIENT CNTFET BASED GDI CELL FOR LOGIC CIRCUITS

The main objectives for today's VLSI circuit designers are designing circuits which occupy less area, consume low power with improved performance. There has always been a tradeoff between these three factors while designing. This work presents a novel idea to satisfy all three factors without a...

Full description

Saved in:
Bibliographic Details
Published in:ARPN journal of engineering and applied sciences 2014-12, Vol.9 (12), p.2794-2798
Main Authors: Monica, P Reena, Sreedevi, V T
Format: Article
Language:English
Subjects:
Carbon nanotubes
Circuit design
Electric power generation
Field effect transistors
Inclusions
Logic circuits
MOSFETs
Unions
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The main objectives for today's VLSI circuit designers are designing circuits which occupy less area, consume low power with improved performance. There has always been a tradeoff between these three factors while designing. This work presents a novel idea to satisfy all three factors without any tradeoff. In this work, Gate Diffusion input (GDI) technique is used along with the high performance Carbon Nanotubes Field Effect Transistor (CNTFET). This union of CNTFET and GDI results in low power, area efficient and high performance logic circuits maintaining less complexity. The layout of the logic circuits are also discussed which shows the inclusion of n-CNTFET and p-CNTFET on the same substrate without the need for a twin tub process as is the requirement in implementing GDI technique using MOSFETs. Thereby a standard cell library has been created for CNTFET based GDI logic circuits. The implementation is carried out in Cadence Virtuoso and Electric, a layout tool.
ISSN:1819-6608
1819-6608