Modeling and analysis of the HPM pulse-width upset effect on CMOS inverter

• Published in: Journal of semiconductors 2015-05, Vol.36 (5), p.66-71
• Main Author: 于新海 柴常春 乔丽萍 杨银堂 刘阳 席晓文
• Format: Article
• Language: English
• Subjects: Carrier density; Carriers; CMOS; CMOS反相器; Computer simulation; Electric potential; HPM; Inverters; Mathematical models; Semiconductors; 密度分布; 建模; 模型推导; 脉冲宽度; 载流子密度; 高功率微波
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/36/5/054011

We derive analytical models of the excess carrier density distribution and the HPM （high-power mi- crowave） upset susceptibility with dependence of pulse-width, which are validated by the simulated results and experimental data. Mechanism analysis and model derivation verify that the excess carriers dominate the current amplification process of the latch-up. Our results reveal that the excess carrier density distribution in P-substrate behaves as pulse-width dependence. The HPM upset voltage threshold Vp decreases with the incremental pulse- width, while there is an inflection point which is caused because the excess carrier accumulation in the P-substrate will be suppressed over time. For the first time, the physical essence of the HPM pulse-width upset effect is pro- posed to be the excess carrier accumulation effect. Validation concludes that the lip model is capable of giving a reliable and accurate prediction to the HPM upset susceptibility of a CMOS inverter, which simultaneously consid- ers technology information, ambient temperature, and layout parameters. From the model, the layout parameter LB has been demonstrated to have a significant impact on the pulse-width upset effect： a CMOS inverter with minor LB is more susceptible to HPM, which enables us to put forward hardening measures for inverters that are immune from the HPM upset.