Device circuit co-design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU M...

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Bibliographic Details
Published in:International journal of numerical modelling 2016-05, Vol.29 (3), p.487-500
Main Author: Rana, Ashwani K.
Format: Article
Language:English
Subjects:
analytical model
Computer simulation
Devices
DIBL
gate tunneling current
Gates (circuits)
HSU MOSFET
Logic circuits
Mathematical models
modified HSU MOSFET
MOSFETs
Nanostructure
spacer dielectrics
Spacers
subthreshold slope
VLSI logic circuit
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Summary:In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.
ISSN:0894-3370
1099-1204
DOI:10.1002/jnm.2099