A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique

This paper proposes a noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. The phase interpolator helps reduce the jitter introduced into the system by the multi-phase generation mechanism used for the fractional operation. The proposed f...

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Bibliographic Details
Main Authors: Narayanan, Aravind Tharayil, Katsuragi, Makihiko, Nakata, Kengo, Terashima, Yuki, Okada, Kenichi, Matsuzawa, Akira
Format: Conference Proceeding
Language:English
Subjects:
Analytical models
Carriers
CMOS
Conferences
Design engineering
Dynamic range
Frequency synthesizers
Jitter
Noise reduction
Phase locked loops
Phase noise
Power consumption
Power demand
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Summary:This paper proposes a noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. The phase interpolator helps reduce the jitter introduced into the system by the multi-phase generation mechanism used for the fractional operation. The proposed frequency synthesizer is fabricated in 65nm CMOS process and it is capable of working at frequencies ranging from 4.3GHz to 4.9GHz. The measured close-in phase noise is -113dBc/Hz at an offset of 200kHz from the carrier with 3.3mW power consumption, which results in a FoM of -246dB.
ISSN:2153-697X
DOI:10.1109/ASPDAC.2016.7427974