An Improved Design of a Reversible Fault Tolerant LUT-based FPGA

This paper presents the design of reversible fault tolerant architecture of logic elements of LUT (look-up table) based Field Programmable Gate Array (FPGA). The proposed logic elements are master slave Flip Flop, D-Latch and multiplexer. A new 4×4 and a new 6×6 fault tolerant reversible gates are p...

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Bibliographic Details
Main Authors: Haque, Mubin Ul, Sworna, Zarrin Tasnim, Babu, Hafiz Md Hasan
Format: Conference Proceeding
Language:English
Subjects:
Delay
Delays
Design engineering
Fault tolerance
Fault tolerant
Fault tolerant systems
Field Programmable Gate Array
Field programmable gate arrays
Gates
Logic
Logic gates
Look-Up Table
Multiplexing
Reversible logic
Table lookup
Transistors
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Summary:This paper presents the design of reversible fault tolerant architecture of logic elements of LUT (look-up table) based Field Programmable Gate Array (FPGA). The proposed logic elements are master slave Flip Flop, D-Latch and multiplexer. A new 4×4 and a new 6×6 fault tolerant reversible gates are proposed for designing efficient reversible fault tolerant D-latch, master slave Flip Flop and multiplexer, respectively. The design of the proposed logic elements achieve the improvement of 41.67% in terms of number of gates compared to the best known existing approach. Besides, the proposed logic elements outperform the best existing technology by 13.33% and 27.27% in terms of quantum cost and unit delay, respectively. Finally, the efficiency of the proposed elements are clarified by implementing an n-bit adder using the proposed Configurable Logic Block (CLB) of FPGA with 60.9% power savings and 23.56% delay minimization.
ISSN:2380-6923
DOI:10.1109/VLSID.2016.39