Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2016-06, Vol.24 (6), p.2208-2219
• Main Authors: Tanakamaru, Shuhei, Hosaka, Shogo, Johguchi, Koh, Takishita, Hirofumi, Takeuchi, Ken
• Format: Article
• Language: English
• Subjects: Acceptability; Ash; Bit error rate; Codes; Data storage; Decoding; Error correction; Error correction codes; Error-correcting code (ECC); Flash memory (computers); Impact analysis; NAND flash memory; Performance evaluation; Reliability; Solid state devices; solid-state drive (SSD); storage-class memory (SCM); Throughput; Very large scale integration; Writing
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2015.2496976

A NAND flash memory/storage-class memory (SCM) hybrid solid-state drive (SSD) can achieve higher performance than the conventional NAND flash-only SSD. Error-correcting codes (ECCs) are applied to the SSD to correct bit errors occurring inside the NAND flash and SCM. To correct more bit errors, the stronger ECC is required and the ECC latency increases. This paper evaluates the relation between the performance and the reliability of the NAND flash/SCM hybrid SSD. First, how the ECC latency impacts the SSD performance is analyzed. Then, the SSD performances are evaluated with various data-access patterns. The ECC effect is significantly different among the data-access patterns. Moreover, four scenarios of the SCM reliability are established and the performances are evaluated with the four data-access patterns. When the SCM reliability becomes high, the decrease in the throughput due to the ECC for SCM becomes significantly small. Finally, by setting the acceptable SSD performance, the acceptable bit-error rate (BER) of the SCM is evaluated. The SCM BER can be as high as around 0.9%.