Practical ILP-based routing of standard cells

This paper proposes a two-stage transistor routing approach that synergizes the merits of channel routing and integer linear programming for CMOS standard cells. It can route 185 cells in 611 seconds. About 21% of cells obtained by our approach have smaller wire length than their handcrafted counter...

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Bibliographic Details
Main Authors: Lu, Hsueh-Ju, Jang, En-Jang, Lu, Ang, Zhang, Yu Ting, Chang, Yu-He, Lin, Chi-Hung, Lin, Rung-Bin
Format: Conference Proceeding
Language:English
Subjects:
Channels
CMOS
Conferences
Design engineering
Electronics
Exhibitions
integer linear programming
Integer programming
Layout
Pins
Rails
Routing
standard cell
transistor
Transistors
Wires
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Summary:This paper proposes a two-stage transistor routing approach that synergizes the merits of channel routing and integer linear programming for CMOS standard cells. It can route 185 cells in 611 seconds. About 21% of cells obtained by our approach have smaller wire length than their handcrafted counterparts. Only 11% of cells use more vias than their handcrafted counterparts. Our router completes routing of many cells that cannot be routed by an industrial one.
ISSN:1558-1101