High-stage analog accumulator for TDI CMOS image sensors

The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate...

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Bibliographic Details
Published in:Journal of semiconductors 2016-02, Vol.37 (2), p.105-115
Main Author: 李建新 黄福军 宗勇 高静
Format: Article
Language:English
Subjects:
Accumulators
Calibration
CMOS
CMOS图像传感器
CMOS技术
Computer simulation
Linearity
Semiconductors
Sensors
TDI
仿真结果
寄生现象
模拟
电荷注入效应
蓄电池
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Summary:The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is em- ployed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature （PVT） variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure.
ISSN:1674-4926
DOI:10.1088/1674-4926/37/2/025001