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Investigation on LDMOS-SCR with high holding current for high voltage ESD protection

We investigate a novel lateral diffused metal-oxide semiconductor (LDMOS) device embedded in silicon controlled rectifier (SCR) and resistance-capacitance circuit (LDMOS-SCR-RC). The internal RC-coupling effect helps to increase the holding current (Ih), resulting in the enhanced latch-up immunity o...

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Bibliographic Details
Published in:Microelectronics and reliability 2016-06, Vol.61, p.120-124
Main Authors: Liang, Hailian, Bi, Xiuwen, Gu, Xiaofeng, Cao, Huafeng, Zhang, Yun
Format: Article
Language:English
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Summary:We investigate a novel lateral diffused metal-oxide semiconductor (LDMOS) device embedded in silicon controlled rectifier (SCR) and resistance-capacitance circuit (LDMOS-SCR-RC). The internal RC-coupling effect helps to increase the holding current (Ih), resulting in the enhanced latch-up immunity of electrostatic discharge (ESD) protection device in high voltage integrated circuits (HV ICs). Transmission line pulse testing results show that the proposed LDMOS-SCR-RC has the largest Ih and smallest trigger voltage (Vt1), comparing to the conventional LDMOS-SCR and LDMOS-SCR embedded a resistance. When key parameters such as the gate-length and resistance are optimized, the Ih increases further from 1.1A to 1.5A, while the Vt1 changes insignificantly. The detailed internal mechanism of LDMOS-SCR-RC with regard to key parameters is analyzed numerically by the SENTAURUS simulation. Results confirm that the increased Ih is mainly due to the enhanced RC-coupling effect. Finally, DC measurements conducted with a semiconductor curve tracer also confirm that the LDMOS-SCR-RC with small device area is effective for avoiding latch-up risks. The optimized LDMOS-SCR-RC provides a useful latch-up immune ESD protection solution for HV ICs input/output ports. •A novel LDMOS-SCR device with internal resistance-capacitance circuit (LDMOS-SCR-RC) is designed to increase the holding current.•ESD characteristics of LDMOS-SCR-RC with different length of the gate and resistance are measured and investigated.•The SENTAURUS simulations confirm that the increased Ih is mainly attributed to the enhanced resistance-capacitance coupling effect. The DC measurements verify that LDMOS-SCR-RC is effective for avoiding latch-up risks.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2016.01.016