A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications

• Published in: Journal of semiconductors 2016-05, Vol.37 (5), p.30-34
• Main Authors: Asthana, Pranav Kumar, Goswami, Yogesh, Ghosh, Bahniman
• Format: Article
• Language: English
• Subjects: band-to-band tunneling (BTBT); Channels; Field effect transistors; Gates; Indium arsenides; junctionless tunnel field effect transistor (JLTFET); Leakage; low power; ratio; Semiconductor devices; Semiconductors; tunnel field effect transistor (TFET); Tunnels (transportation); 场效应晶体管; 应用; 本征通道; 等离子体; 纳米级; 装置结构; 超低功耗; 隧道
• ISSN: 1674-4926
• DOI: 10.1088/1674-4926/37/5/054002

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.