A programmable method for low-power scan shift in SoC integrated circuits

We present a programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing. An SoC design is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift....

Full description

Saved in:
Bibliographic Details
Main Authors: Ran Wang, Bhaskaran, Bonita, Natarajan, Karthikeyan, Abdollahian, Ayub, Narayanun, Kaushik, Chakrabarty, Krishnendu, Sanghani, Amit
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Boundaries
Clocks
Design analysis
Design engineering
Heuristic algorithms
Integrated circuits
Mathematical model
Mathematical models
Optimization
Power supplies
Rails
System on chip
Testing
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We present a programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing. An SoC design is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks. The positions of all blocks are first analyzed and the shared boundary length between blocks is then calculated. Based on the position relationships between the blocks, a mathematical model is presented to derive optimal result for small-to-medium sized problems. For larger designs, a heuristic algorithm is proposed and evaluated. We present assignment results as well as power-analysis results and silicon data for industry designs to highlight the effectiveness of the proposed method.
ISSN:2375-1053
DOI:10.1109/VTS.2016.7477289