Drop failure modes of Sn–3.0Ag–0.5Cu solder joints in wafer level chip scale package

To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn–3.0Ag–0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board...

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Bibliographic Details
Published in:Transactions of Nonferrous Metals Society of China 2016-06, Vol.26 (6), p.1663-1669
Main Authors: HUANG, Ming-liang, ZHAO, Ning, LIU, Shuang, HE, Yi-qian
Format: Article
Language:English
Subjects:
Chips
Circuit boards
drop failure mode
Failure modes
Fracture mechanics
Impact tests
Packages
Printed circuits
Sn–3.0Ag–0.5Cu
solder joint
Solders
Tin base alloys
wafer level chip scale package
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Summary:To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn–3.0Ag–0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board (PCB) side, split between redistribution layer (RDL) and Cu under bump metallization (UBM), RDL fracture, bulk cracks and partial bulk and intermetallic compound (IMC) cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.
ISSN:1003-6326
DOI:10.1016/S1003-6326(16)64272-3