Suitability of N-ON Recessed Implanted Gate Vertical-Channel SiC JFETs for Optically Triggered 1200 V Solid-State Circuit Breakers

• Published in: IEEE journal of emerging and selected topics in power electronics 2016-09, Vol.4 (3), p.874-879
• Main Authors: Veliadis, Victor, Steiner, B., Lawson, K., Bayne, S. B., Urciuoli, D., Ha, H. C.
• Format: Article
• Language: English
• Subjects: 1200 V; bidirectional; Circuit breakers; Circuits; Electric potential; Electronics; fault isolation; four quadrant; Gates (circuits); hard switching; high temperature; high voltage; JFET; JFETs; Logic gates; Nickel; normally ON (N-ON); pulsing; reliability; RLC circuits; Semiconductor devices; SiC; Silicon carbide; solid-state circuit breaker (SSCB); Switches; Switching circuits
• ISSN: 2168-6777; 2168-6785
• DOI: 10.1109/JESTPE.2016.2583430

A requirement for the commercialization of power SiC transistors is their long term reliable operation under the hard-switching conditions and high temperatures encountered in the field. Normally ON 1200 V vertical-channel implanted-gate SiC junction field effect transistors (JFETs), designed for highpower bidirectional (four quadrant) solid-state-circuit-breaker (SSCB) applications, were repetitively pulse hard switched at 150 °C from a 1200 V blocking state to an ON-state current of 115 A, which is in excess of 13 times the JFET's 250-W/cm 2 rated current at 150 °C. The JFETs were fabricated in seven photolithographic levels with a single masked ion-implantation forming the p+ gates and guard rings, and with no epitaxial regrowth. The pulsed testing was performed using a low inductance RLC circuit. In this circuit, energy initially stored in a capacitor is discharged in a load resistor through the JFET under test. The JFET hard-switch stressing included over 2.4 million 1200 V/115-A hard-switch events at 150 °C and at a repetition rate of 10 Hz. The peak energies and powers dissipated by the JFET at each hard-switch event were 73.2 mJ and 68.2 kW, respectively. The current rise rate was 166 A/μs and the pulse full width at half maximum (FWHM) was 1.8 μs. After over 2.4 million hard-switch events at 150 °C, the JFET blocking voltage characteristics remained unchanged while the ON-state conduction slightly improved, which indicate reliable operation. An optically triggered SSCB, based on these rugged JFET, is proposed.