A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method

Modern wireless communication standards define new high-throughput use cases like 8 x 8 multiple-input, multipleoutput (MIMO) antenna setups and a 256-QAM constellation alphabet in the case of IEEE 802.11ac. Baseband precoding at the transmitter is a key technique to achieve the corresponding data r...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2016-08, Vol.63 (8), p.1283-1294
Main Authors: Guenther, Daniel, Leupers, Rainer, Ascheid, Gerd
Format: Article
Language:English
Subjects:
Algorithms
Alphabets
Application specific integrated circuits
Application-specific integrated circuit (ASIC)
Computation
Computer architecture
Constellations
Hardware
IEEE 802.11ac
Jacobian matrices
Matrix decomposition
MIMO
MIMO (control systems)
multimode
multiple input
multiple output (MIMO)
Precoding
Reduction
Singular value decomposition
singular value decomposition (SVD)
Wireless communication
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Summary:Modern wireless communication standards define new high-throughput use cases like 8 x 8 multiple-input, multipleoutput (MIMO) antenna setups and a 256-QAM constellation alphabet in the case of IEEE 802.11ac. Baseband precoding at the transmitter is a key technique to achieve the corresponding data rates at a reasonable signal-to-noise ratio (SNR). Multimode capability, (i.e., the ability to support multiple MIMO setups) is crucial for legacy compatibility or for the adaptation to the individual configurations of mobile stations. This paper presents an application-specific integrated circuit (ASIC) template for singular value decomposition (SVD)-based linear precoding supporting multimode MIMO. A two-sided cyclic Jacobi algorithm is applied to decompose the SVD computation exclusively into 2 x 2 vector arithmetic units. A fixed computation pattern is executed iteratively on the input data. Iteration control allows a graceful trading of communication performance for a reduction of computational complexity. As a proof-of-concept, the architecture template is configured to support 2 x 2, 4 x 4, 6 x 6, and 8 x 8 MIMO and is layouted for 90-nm CMOS with a core area of 1.34 mm 2 and a clock frequency of 752 MHz. The achieved throughput is 188, 15.7, 6.27, and 1.68 million SVDs per second, respectively.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2016.2561904